PIC18F4539T-E/ML【PDF 146/322 页】IC PIC MCU FLASH 12KX16 44QFN

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2002 Microchip Technology Inc.

Preliminary

DS30485A-page 21

PIC18FXX39

FIGURE 2-5:

PLL BLOCK DIAGRAM

2.5

Effects of SLEEP Mode on the

On-Chip Oscillator

When the device executes a SLEEP instruction, the

oscillator is turned off and the device is held at the

beginning of an instruction cycle (Q1 state). With the

oscillator off, the OSC1 and OSC2 signals will stop

oscillating. Since all the transistor switching currents

have been removed, SLEEP mode achieves the lowest

current consumption of the device (only leakage cur-

rents). Enabling any on-chip feature that will operate

during SLEEP will increase the current consumed dur-

ing SLEEP. The user can wake from SLEEP through

external RESET, Watchdog Timer Reset, or through an

interrupt.

2.6

Power-up Delays

Power-up delays are controlled by two timers, so that

no external RESET circuitry is required for most appli-

cations. The delays ensure that the device is kept in

RESET, until the device power supply and clock are

stable. For additional information on RESET operation,

see Section 3.0.

The first timer is the Power-up Timer (PWRT), which

optionally provides a fixed delay of 72 ms (nominal) on

power-up only (POR and BOR). The second timer is

the Oscillator Start-up Timer (OST), intended to keep

the chip in RESET until the crystal oscillator is stable.

With the PLL enabled (HS/PLL Oscillator mode), the

time-out sequence following a Power-on Reset is differ-

ent from other Oscillator modes. The time-out

sequence is as follows:

The PWRT time-out is invoked after a POR time

delay has expired.

The Oscillator Start-up Timer (OST) is invoked.

However, this is still not a sufficient amount of

time to allow the PLL to lock at high frequencies.

The PWRT timer is used to provide an additional

fixed 2 ms (nominal) time-out to allow the PLL

ample time to lock to the incoming clock

frequency.

TABLE 2-2:

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

MUX

VCO

Loop

Filter

÷4

Crystal

Osc

OSC2

OSC1

PLL Enable

FIN

FOUT

SYSCLK

Phase

Comparator

(from Configuration

HS Osc

bit Register)

OSC Mode

OSC1 Pin

OSC2 Pin

ECIO

Floating

Configured as PORTA, bit 6

Floating

At logic low

Feedback inverter disabled, at quiescent

voltage level

Feedback inverter disabled, at quiescent

voltage level

Note:

See Table 3-1 in the “Reset” section, for time-outs due to SLEEP and MCLR Reset.

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